`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/11/11 11:32:59
// Design Name: 
// Module Name: reader
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module reader(
    input clk,  // 100 MHz timer input
    input [7:0] d_i,
    output reg [3:0] highdigit_o,
    output reg [3:0] lowdigit_o
    );
    
    wire clk_200hz;
    divider_200hz DIVIDER(clk, 1'b0, clk_200hz);
    wire clk_200hz_n = ~clk_200hz;
    
    reg [7:0] d_pos;
    reg [7:0] d_neg;
    wire [7:0] d_xor;
    
    always @(posedge clk_200hz) begin
        d_pos <= d_i;
    end
    
    always @(posedge clk_200hz_n) begin
        d_neg <= d_i;
    end
    
    always @(d_xor) begin
        
    end
endmodule
